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Tezzaron Cuts Design Time in Half with Cadence Full-Flow Digital RTL-to-Signoff Solution

SAN JOSE, Calif., May 9, 2016 /PRNewswire/ -- Cadence Design Systems, Inc. CDNS, +1.90% today announced that Tezzaron Semiconductor has adopted the Cadence® full-flow digital register-transfer level (RTL)-to-signoff solution for its networking and supercomputing system on chips (SoCs), cutting its development schedules in half. Tezzaron, best known for 3D-ICs and advanced memory devices, has incorporated Cadence tools in its design work from the very beginning. Over the years, Tezzaron's products have increased in size, sophistication and complexity, prompting the adoption of the full-flow solution.

For more information on the Cadence full-flow digital RTL-to-signoff solution, please visit www.cadence.com/news/tezzaron.

"Our high-performance 3D SoCs really push the limits," said Anita Rao, VP of engineering at Tezzaron. "High bandwidth, low power, extreme performance—the Cadence flow gives us the tools we need to create these designs quickly and accurately. We have seen huge gains in productivity."

Chip designers strive for low power, high performance and small area—collectively known as 'PPA'. 3D-ICs typically demonstrate increased performance in a smaller footprint and their short vertical interconnects dramatically reduce...


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