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Fuji Xerox Reduces Silicon Area by More than 50 Percent Using Synopsys ASIP Designer


  • Fuji Xerox reduced silicon area by more than 50 percent using an application-specific instruction set processor (ASIP) developed with ASIP Designer, compared to fixed hardware
  • ASIP Designer's 'compiler-in-the-loop' technology enabled use of application code to optimize the processor architecture for performance, power and area
  • Automatic generation of software development kit and synthesizable RTL enabled Fuji Xerox to complete the entire design in less than 14 months

Synopsys, Inc. (Nasdaq:SNPS) today announced Fuji Xerox Co., Ltd. used Synopsys' ASIP Designer tool to design a high-performance application-specific instruction set processor (ASIP) for its full-color multifunction printer. With ASIP Designer, Fuji Xerox developed a specialized instruction-set custom processor that consumed less than 50 percent of the die area of a fixed hardware implementation while still meeting the performance requirements. In addition, unlike fixed hardware, an ASIP offers software programmability, providing the flexibility Fuji Xerox needed to meet the varied processing demands of its multifunction printer application. Using ASIP Designer, Fuji Xerox's design team was able to complete its ASIP design from concept to implementation in less than14 months.

'Synopsys' reputation as the premier provider of ASIP development tools was the key factor in our decision to use ASIP Designer for our custom processor development,' said Noriaki Tsuchiya, manager of the Controller Development Group at Fuji Xerox Co., Ltd. 'ASIP Designer's rapid architectural...